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8M x 8-Bit Dynamic RAM (4k & 8k Refresh, EDO-version)
HYB 3164805BJ/BT(L) -40/-50/-60 HYB 3165805BJ/BT(L) -40/-50/-60
Premininary Information
* * * *
8 388 608 words by 4-bit organization 0 to 70 C operating temperature Hyper Page Mode - EDO - operation Performance: -40 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/write cycle time Hyper page mode (EDO) cycle time 40 10 20 69 16 -50 50 13 25 84 20 -60 60 15 30 104 25 ns ns ns ns ns
* *
Single + 3.3 V ( 0.3V) power supply Low power dissipation: max. 306 active mW ( HYB 3164805BJ/BT(L)-40) max. 252 active mW ( HYB 3164805BJ/BT(L)-50) max. 216 active mW ( HYB 3164805BJ/BT(L)-60) max. 486 active mW ( HYB 3165805BJ/BT(L)-40) max. 396 active mW ( HYB 3165805BJ/BT(L)-50) max. 324 active mW ( HYB 3165805BJ/BT(L)-60) 7.2 mW standby (LVTTL) 3.6 mW standby (LVMOS) 720 A standby for L-version Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh
*
Self refresh (L-version only) 8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164805BJ/BT) 4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165805BJ/BT) * 128 msec refresh period for L-versions * Plastic Package: P-SOJ-32-1 400 mil HYB 3164(5)400BJ P-TSOPII-32-1 400 mil HYB 3164(5)400BT(L)
* *
Semiconductor Group
1
12.97
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
This HYB3164(5)805B is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in SIEMENS'most advanced 0,25 m-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)805B operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)400B to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)805BTL parts have a very low power leep mode"supported by Self Refresh. s Ordering Information Type 8k-refresh versions: HYB 3164805BJ-40 HYB 3164805BJ-50 HYB 3164805BJ-60 HYB 3164805BT-40 HYB 3164805BT-50 HYB 3164805BT-60 HYB 3164805BTL-50 HYB 3164805BTL-60 4k-refresh versions: HYB 3165805BJ-40 HYB 3165805BJ-50 HYB 3165805BJ-60 HYB 3165805BT-40 HYB 3165805BT-50 HYB 3165805BT-60 HYB 3165805BTL-50 HYB 3165805BTL-60 P-SOJ-32-1 P-SOJ-32-1 P-SOJ-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 400 mil DRAM (access time 40 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) 400 mil DRAM (access time 40 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) P-SOJ-32-1 P-SOJ-32-1 P-SOJ-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 400 mil DRAM (access time 40 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) 400 mil DRAM (access time 40 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) 400 mil DRAM (access time 50 ns) 400 mil DRAM (access time 60 ns) Ordering Code Package Descriptions
Semiconductor Group
2
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
P-SOJ-32-1 (400 mil) P-TSOPII-32-1 (400 mil)
VCC I/O1 I/O2 I/O3 I/O4 N.C. VCC WE RAS . A0 A1 A2 A3 A4 A5 VCC
O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS I/O8 I/O7 I/O6 I/O5 VSS CAS OE A12 / N.C. * A11 A10 A9 A8 A7 A6 VSS
* Pin 24 is A12 for HYB 3164805BJ/BT(L) and N.C. for HYB 3165805BJ/BT(L) Pin Configuration Pin Names A0-A12 A0-A11 RAS OE I/O1-I/O8 CAS WE Vcc Vss Address Inputs for 8k-refresh version HYB 3164805BJ/BT(L) Address Inputs for 4k-refresh version HYB 3165805BJ/BT(L) Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground
Semiconductor Group
3
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
TRUTH TABLE
FUNCTION Standby Read Early-Write Delayed-Write Read-Modify-Write Hyper Page Mode Read 1st Cycle 2nd Cycle Hyper Page Mode Write 1st Cycle 2nd Cycle Hyper Page Mode RMW 1st Cycle 2st Cycle RAS only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh READ WRITE Self Refresh (L-version only)
RAS H L L L L L L L L L L L H-L H-L L-H-L L-H-L H-L
CAS H-X L L L L H-L H-L H-L H-L H-L H-L H L L L L L
WE X H L H-L H-L H H L L H-L H-L X H L H L H
OE X L X H L-H L L X X L-H L-H X X X L X X
ROW ADDR X ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW X X ROW ROW X
COL ADDR X COL COL COL COL COL COL COL COL COL COL n/a n/a n/a COL COL X
I/O1I/O4 High Impedance Data Out Data In Data In Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance High Impedance Data Out Data In High Impedance
Semiconductor Group
4
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
I/O1 I/O2
I/O8
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator 8
Data out Buffer
8
OE
10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Column Address Buffer(10)
10
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
8
Refresh Counter (13) 13 Row 13
1024 x8
Address Buffers(13)
13
Decoder 8192
Row
Memory Array 8192 x 1024 x 8
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3164805BJ/BT(L)
Semiconductor Group
5
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
I/O1 I/O2
I/O8
WE CAS
.
&
Data in Buffer
No. 2 Clock Generator 8
Data out Buffer
8
OE
11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
12
Column Address Buffer(11)
11
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
8
Refresh Counter (12) 12 Row
2048 x8
Address Buffers(12)
12
Decoder 4096
Row
Memory Array 4096 x 2048 x 8
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3165805BJ/BT(L)
Semiconductor Group
6
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
Absolute Maximum Ratings Operating temperature range.............................................................................................. 0 to 70 C Storage temperature range......................................................................................... - 55 to 150 C Input/output voltage.................................................................................. -0.5 to min (Vcc+0.5,4.6) V Power supply voltage.................................................................................................... -0.5V to 4.6 V .....0.62 W ..50 mA
Power dissipation...............................................................................................................
Data out current (short circuit)................................................................................................
Note
Stresses above those listed under bsolute Maximum Ratings"may cause permanent damage of A the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output "level voltage (Iout = -2mA) H Output low voltage (LVTTL) Output "evel voltage (Iout = +2mA) Ll Output high voltage (LVCMOS) Output "level voltage (Iout = -100uA) H Ouput low voltage (LVCMOS) Output " level voltage (Iout = +100uA) L Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 0.2 2 2 2.0 - 0.3 2.4 - Vcc-0.2 -2 -2
Unit Note V V V V V V A A 1) 1)
VIH VIL VOH VOL VOH VOL II(L) IO(L)
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
Semiconductor Group
7
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
DC-Characteristics (cont' ) d
TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V
Parameter Operating Current -40 ns version -50 ns version -60 ns version Symbol refresh version Unit Note 4k row 8k row 85 70 60 2 85 70 60 mA mA mA mA mA mA mA 2) 3) 4)
ICC1
135 110 90
-
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Current (RAS=CAS= Vih) RAS Only Refresh Current: -40 ns version -50 ns version -60 ns version
ICC2 ICC3
2 135 110 90
- 2) 4)
(RAS cycling: CAS = VIH: tRC = tRC min.)
Hyper Page Mode (EDO) Current: ICC4 -40 ns version -50 ns version -60 ns version
(RAS = VIL, CAS, address cycling: tHPC=tHPC min.)
100 65 45 1 200
100 65 45 1 200
mA mA
2) 3) 4)
Standby Current
(RAS=CAS= Vcc-0.2V)
ICC5 ICC5
mA A
- -
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
ICC6 CAS Before RAS Refresh Current -40 ns version -50 ns version -60 ns version
(RAS, CAS cycling: tRC = tRC min.)
135 110 90 400
85 70 60 400
mA mA
2) 4)
Self Refresh Current (L-version only)
(CBR cycle with tRAS>TRASSmin, CAS held low, WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
ICC7
A
Capacitance TA = 0 to 70 C,VCC = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (A0 to A11,A12) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1-I/O8) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
8
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter
Symbol
AC64-2E
Limit Values min.
Unit
Note
40
max.
- 50
min. max.
- 60
min. max.
Common Parameters
Random read or write cycle time RAS pulse width CAS pulse width RAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) tRC tRAS tCAS tRP tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT 69 40 6 25 6 0 5 0 5 9 7 6 32 5 1 - - - -
100k 100k
84 50 8 30 8 0 7 0 7 11 9 8 40 5 1 - - -
-
100k 100k
104 60 10 40 10 0 10 0 10 14 12 10 48
-
100k 100k
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms 7
- - - - - - 30 20 - - - 50 128 64 128
- - - - - - 37 25
- - - - - - 45 30 - - - 50 128 64 128
- 50 128 64 128
5 1 - - -
Refresh period for 8k-refresh-version tREF Refresh period for 4k-refresh version tREF Refresh period for L-versions tREF
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time tRAC tCAC tAA tOEA tRAL tRCS tRCH - - - - 20 0 0 40 10 20 10 - - - - - - - 25 0 0 50 13 25 13 - - - - - - - 30 0 0 60 15 30 15 - - - ns ns ns ns ns ns ns 11 8, 9 8, 9 8,10
Semiconductor Group
9
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
AC Characteristics (cont' ) 5)6) d TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter
Symbol
AC64-2E
Limit Values min.
Unit
Note
40
max.
- 50
min. max.
- 60
min. max.
Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay
tRRH tCLZ tOFF tDZC tDZO tCDD tODD
0 0 0 0 0 0 10 10
- - 10 10 - - - -
0 0 0 0 0 0 13 13
- - 13 13 - - - -
0 0 0 0 0 0 15 15
- - 15 15 - - - -
ns ns ns ns ns ns ns ns
11 8 12 12 13 13 14 14
Output buffer turn-off delay from OE tOEZ
Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 5 5 0 6 6 0 5 - - - - - - - 7 7 0 8 8 0 7 - - - - - - - 10 10 0 10 10 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 89 52 22 32 5 - - - - - 109 65 28 40 7 - - - - - 133 77 32 47 10 - - - - - ns ns ns ns ns 15 15 15
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time Access time from CAS precharge Output data hold time tHPC tCPA tCOH 16 - 3 - 22 - 20 - 5 - 27 - 24 - 5 - 32 - ns ns ns 7
Semiconductor Group
10
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
AC Characteristics (cont' ) 5)6) d TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter
Symbol
AC64-2E
Limit Values min.
Unit
Note
40
max. 200k
- 50
min. max. 200k
- 60
min. max. 200k
RAS pulse width in hyper page mode tRAS CAS precharge to RAS Delay OE pulse width OE hold time from CAS high OE setup time prior to CAS tRHPC tOEP tOEHC tOES
40 22 5 5 0 5
50 27 5 5 0 5
60 32 5 5 0 5
ns ns ns ns ns ns
- - - 10 -
- - - 13 -
- - - 15 -
Output buffer turn-off delay from WE tWEZ
Hyper Page Mode (EDO) Readmodify-Write Cycle
Hyper page mode (EDO) read-write cycle time CAS precharge to WE tPRWC tCPWD 44 34 - - 54 42 - - 63 49 - - ns ns
CAS before RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 5 5 5 5 5 - - - - - 5 5 5 5 5 - - - - - 5 10 5 10 10 - - - - - ns ns ns ns ns
Self Refresh Cycle (L-versions only)
RAS pulse width RAS precharge time CAS hold time tRASS tRPS tCHS
100k 100k
_ - -
100k
_ - -
ns ns ns
17 17 17
69 -50
- -
84 -50
104 -50
Test Mode Cycle
Write command setup time Write command hold time tWTS tWTH 5 5 - - 5 5 - - 5 5 - - ns ns 18 18
Semiconductor Group
11
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
Notes:
1) All voltages are referenced to VSS. Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. 2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = Vil. In the case of ICC4 it can be changed once or less during a hyper page mode cycle ( thpc). 5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh. If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh 18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value. These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must be adjusted by 5 ns.
Semiconductor Group
12
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column
tASR
Row
Address
V IH VIL
Row
tRCH tRAH tRCS tRRH tAA tOEA
WE
V IH VIL
OE
V IH VIL
tDZC tDZO tCAC tCLZ
Hi Z
tCDD tODD
I/O (Inputs)
V IH VIL
tOFF tOEZ
Valid Data Out Hi Z
I/O (Outputs) V
V OH OL
tRAC
" " or " " H L
WL1
Read Cycle
Semiconductor Group
13
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
V IH
CAS
VIL
tRAD tASR tASC
tASR
. Row
Address
V IH VIL
Row
tRAH
WE
V IH VIL
tWCS tWP
tCWL
tWCH tRWL
OE
V IH VIL
tDS
I/O (Inputs)
V IH VIL
tDH
Valid Data In
OH I/O (Outputs) V OL
V
Hi Z
" " or " " H L
WL2
Write Cycle (Early Write)
Semiconductor Group
14
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column
tASR
Row
V IH
.
Address V IL
Row
tRAH
WE
V IH VIL
tCWL tRWL tWP
tOEH
OE
V IH VIL
tDZO tDZC
I/O (Inputs)
V IH VIL
tODD tDS tOEZ tCLZ tOEA
tDH
Valid Data
OH I/O (Outputs) V OL
V
Hi-Z
Hi-Z
" " or " " H L
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
15
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRWC tRAS
V IH VIL V IH
tRP
RAS
tCSH tRCD tRSH tCAS tCRP
CAS
VIL
tRAH tASR
Address
V IH VIL Row
tCAH tASC
Column
tASR
Row
tRAD
V IH
tAWD tCWD tRWD
tCWL tRWL tWP
WE
VIL
tAA tRCS
V IH
tOEA
tOEH
OE
VIL
tDZO tDZC
I/O (Inputs)
V IH VIL
tDS tDH
Valid Data in
tCLZ tCAC
tODD tOEZ
Data Out
I/O (Outputs) V OL
V OH
tRAC
" " or " " H L
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
16
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRAS
RAS
V IH VIL
tRP tRHPC tRSH tCRP
tRCD
tHPC tCRP
V IH
tCAS
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC
Row
tRAL tCAH tASC tCAH
Column 2
tASC tCAH
Column N
Address
V IH VIL Column 1
tRAD tRRH tRCH
tRCS
WE
VIH VIL
tOES
OE
V OH V OL
tCAC tAA tCPA
tCAC tAA tCPA
tOFF
tOEA tRAC tAA tCAC
tOEZ tCOH tCOH
Data Out 2 Data Out N
I/O IH (Output) V IL
V
tCLZ
Data Out 1
" " or " " H L
WL5
Hyper Page Mode (EDO) Read Cycle Semiconductor Group 17
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRAS
V IH
tRP tRHCP tRSH
tRCD
RAS
VIL
tHPC tCRP
V IH
tCRP
tCAS
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC
Row
tRAL tCAH tASC tCAH
Column 2
tASC tCAH
Column N
Address
V IH VIL Column 1
tRAD tRRH tRCH tCAC tAA tCPA tOEHC tOEHC tCAC tAA tCPA
tRCS
WE
VIH VIL
tOES
V OH V OL
tOFF
tOEA tRAC tAA tCAC
OE
tOEP tOEZ
tOEA
tOEP tOEA tOEZ tOEZ
Data Out 2
I/O IH (Output) V IL
V
tCLZ
Data Out 1 Data Out N
WL6
" " or " " H L
Hyper Page Mode (EDO) Read Cycle (OE Control)
Semiconductor Group
18
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRAS
V IH
tRP tRHPC tRSH
tRCD
RAS
VIL
tCRP
V IH
tHPC tCAS
tCRP
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC
Row
tRAL tCAH tASC tCAH
Column 2
tASC tCAH
Column N
Address
V IH VIL Column 1
tRAD
tAA
tAA tRCH tRRH tRCH tRCS
tRCS
WE
VIH VIL
tRCH
tRCS
tWP tOES
OE
V OH V OL
tCAC tCPA
tWP
tCAC tCPA tOFF
tOEA tRAC tAA tCAC
tOEZ tWEZ tWEZ
I/O IH (Output) V IL
" " or " " H L
V
tCLZ
Data Out 1 Data Out 2 Data Out N
WL7
Hyper Page Mode (EDO) Read Cycle (WE Control)
Semiconductor Group
19
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRAS
V IH
tRP tRHPC tRSH tCRP
tRCD
RAS
VIL
tCRP
V IH
tHPC tCAS
tCP
tCAS
tCAS
CAS
VIL
tCSH tASR tRAH tASC
Row Addr
tRAL tCAH tASC tCAH
Column 2
tASC tCAH
Column N
Address
V IH VIL
Column 1
tRAD tCWL tWCS
VIH VIL
tCWL tWCH tWP tWCS
tRWL tCWL tWCH tWP
tWCH tWCS tWP
WE
OE
V OH V OL
tDS
V IH
tDH
tDS
tDH
tDS
tDH
I/O (Input) V IL
Data In 1
Data In 2
Data In N
" " or " " H L
WL8
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
20
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRAS
V IH
tRP
tRCD tRSH tCP tCAS tCP tCAS
RAS
VIL
tHPC tCRP
V IH
tCRP
tCAS
CAS
VIL
tCSH tASR tRAH tASC
Row
tRAL tCAH tASC tCAH
Column 2
tASC tCAH
Column N
Address
V IH VIL Column 1
tRAD
tCWL tRCS
tCWL tRCS
tCWL tRWL
tRCS
WE
VIH VIL
tWP tOEH
OE
V OH V OL
tWP tOEH
tWP tOEH
tODD tDS tODD tDH tDS tDH
tODD tDS tDH
I/O (Input)
V IH VIL
Data In 1
Data In 2
Data In N
WL16
" " or " " H L
Hyper Page Mode (EDO) Late Write Cycle
Semiconductor Group
21
tRASP tRP tPRWC tCP tCAS tCAS tCAH tASC tASC
Column Row Column
V
RAS
IH
V IL
tCSH tRSH tCAS tRAL tCRP
tRCD
Semiconductor Group
V
CAS
IH
V IL
tASR tASC
Column
tRAD tRAH tCAH tCAH
tASR
V
Address
IH
V IL
Row
V
tRCS tAWD tOEA tOEA tWP tWP tOEA tAWD tAWD
tRWD tCWD tCWL tCWL
tCPWD tCWD
tCPWD tCWD
tRWL tCWL
WE
IH
Hyper Page Mode (EDO) Read-Modify-Write Cycle
V IL
22
tAA
tWP
V
OE
IH
V IL
tCPA tDZC
Data In Data In
tCPA tODD tDZC tCLZ tOEH tOEZ tDS
Data Out Data Out
V
IH
tDZC tCLZ tDZO tCLZ tCAC tRAC tOEZ tDH tAA tDS
Data Out
tODD
Data In
I/O (Inputs) V IL
tODD
tOEH tDH
tOEH tCAC tAA tDS tDH
OH I/O (Outputs) V
V
OL
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
WL17
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCRP tRPC
V IH
CAS
VIL
tRAH tASR
tASR
Row
Address
V IH VIL
Row
OH I/O (Outputs) V OL
V
HI-Z
" " or " H L"
WL9
RAS Only Refresh Cycle
Semiconductor Group
23
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRC tRP
RAS
V IH VIL
tRAS
tRP
tRPC tCP
tCSR tCHR tRPC
tCRP
CAS
V IH VIL
tWRP tWRH
V IH VIL
WE
tOEZ
OE
V IH VIL
tCDD
I/O (Inputs)
V IH VIL
tODD
OH I/O (Outputs) VOL V
HI-Z
tOFF
" " or " " H L
WL10
CAS-before-RAS Refresh Cycle
Semiconductor Group
24
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRC
V IH VIL
tRC tRP tRAS tRP
tRAS
RAS
tRCD
V IH VIL
tRSH tCHR tCRP
CAS
tRAD tASC tASR tRAH
Row
tWRP tCAH tWRH tASR
Row
Address
V IH VIL
Column
tRCS
WE
V IH VIL
tRRH
tAA tOEA
OE
V IH VIL
tDZC tDZO
tCDD tODD tCAC tCLZ
I/O (Inputs)
V IH VIL
tOFF tOEZ
Valid Data Out HI-Z
tRAC
OH I/O (Outputs) V OL V
" or " " H" L
WL11
Hidden Refresh Read Cycle
Semiconductor Group
25
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRC tRP
RAS
V IH VIL
tRC tRP tRAS
tRAS
tRCD
V IH VIL
tRSH
tCHR
tCRP
CAS
tRAD tRAH tASR tASC tCAH
Column
tASR
Row
Address
V IH VIL
Row
tWCS
tWCH tWP
tWRP
tWRH
WE
V IH VIL
tDS
I/O (Input)
V IH V IL
tDH
Valid Data
OH I/O (Output) V OL
V
HI-Z
" " or " " H L
WL12
Hidden Refresh Early Write Cycle
Semiconductor Group
26
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRP
RAS
V IH VIL
tRASS
tRPS
tRPC tCSR
CAS
V IH VIL
tCHS
tCRP
tCP
tWRP tWRH
WE
V IH VIL
OE
V IH VIL
tCDD
I/O (Inputs)
V IH VIL
tODD tOEZ
OH I/O (Outputs) V OL
V
HI-Z
tOFF
" " or " " H L
WL13
Self Refresh (Sleep Mode)
Semiconductor Group
27
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
tRP
RAS
V IH VIL
tRC tRAS tRP
tRPC tCP tCSR tCHR tRPC tCRP
CAS
V IH VIL
tASR tRAH
Address IH
VIL V
Row
tWTS
WE
V IH VIL
tWTH
OE
V IH VIL
I/O (Inputs) V IL
V IH
tODD
HI-Z
tCDD tOEZ
I/O (Outputs) V OL
V OH
HI-Z
tOFF
" " or " " H L
WL15
Test Mode Entry Cycle
Semiconductor Group
28
HYB3164(5)805BJ/BT(L)-40/-50/-60 8M x 8-DRAM
Package Outlines Plastic Package P-SOJ-32-1 (400 mil) (Small Outline J-lead, SMD)
Plastic Package P-TSOPII-32-1 (400 mil) (Small Outline J-lead, SMD)
Semiconductor Group
29

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